Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate
Patent
1996-08-26
1998-10-06
Bowers, Jr., Charles L.
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
By reaction with substrate
438773, H01L 21316
Patent
active
058175814
DESCRIPTION:
BRIEF SUMMARY
The invention relates to a process for making an SiO.sub.2 layer by thermal oxidation and in particular to a reproducible process which assures an extremely uniform thickness of the SiO.sub.2 layer.
Thermally oxidizing silicon surfaces is one of the key process steps for manufacturing micromechanical as well as semiconductor devices. In the semiconductor manufacturing process sequence the critical oxidation step is producing the gate oxide layer for field effect transistors. These extremely thin oxide layers, a typical thickness range is 10 nm to 20 nm, have to fulfill high quality requirements and therefore the thermal oxidation for these layers is done with dry oxygen which provides the known small oxidation rate. Using dry oxidation thickness uniformities of these thin layers which are in the range of about 1% to 4% may be achieved.
For thin oxide layers the slow dry oxidation may be tolerable, but not for oxide layers in the range from 0.1 .mu.m up to several .mu.m which are usual for the silicon-on-insulator technology and for various types of micromechanical devices like e.g. calibration standards as disclosed in the application EP 94 10 5568 filed Apr. 11, 1994.
Especially for the calibration standard the uniformity of the silicon oxide layer should be as best as possible since it directly affects the accurateness of the standard.
Variations in either the temperature or wetness of the various wafers which are being processed, caused by variations in the cleaning procedure and/or the air to which the wafers are exposed, cause variations in the rate of initial heating and oxidation of the wafers and thereby cause significant large variations in the amount of oxide growth, especially in the spontaneous oxide layer. To eliminate these effects in U.S. Pat. No. 3,892,891 the wafers are pre-heated at a moderate temperature, e.g. in the range between 100.degree. and 200.degree. C., in a controlled atmosphere, e.g. air having a controlled dew point.
Todays' furnace manufacturer guarantee uniformities of 1% for dry oxygen and 2.5% for wet oxygen processes. Assuming a desired layer thickness of 1 .mu.m this would mean uniformity differences of about 10 nm to 30 nm which is not sufficient for e.g. micromechanical calibration standards.
It is an object of the present invention to provide a reproducible process for the creation of a thermal SiO.sub.2 layer which shows an extreme uniformity in the layer thickness of approximately 1%.
FIG. 1 illustrates an example for the thickness variation of a silicon oxide layer.
FIG. 2 illustrates a temperature/time profile of a preferred process sequence.
The process of the invention comprises the steps growing an initial layer of SiO.sub.2 to a defined minimal thickness by dry oxidation and increasing the thickness of the initial layer by simultaneous wet and dry oxidation until the desired final thickness is reached.
This process offers the possibility to reproducibly manufacture relatively thick oxide layers with uniformities better than oxide layers of the same thickness made with dry oxygen only. The uniformity of oxide layers produced according to the claimed process and having a thickness of 0.5 .mu.m was .+-.0.37 nm along a 50 mm diameter line in the center of a 100 mm wafer. An example for the thickness variation of a 0.5 .mu.m silicon oxide layer is given in FIG. 1.
Further preferable solutions and embodiments are apparent from the dependent claims.
One way of carrying out the invention is described in detail below with reference to FIG. 2 which shows the temperature/time profile of a special process sequence.
In FIG. 2 there is shown the temperature/time profile of a preferred process sequence of the invention with the various phases 0 to 15.
Phase 0 represents the loading of the oxidation chamber, which typically is a quartz tube, with semiconductor wafers or other substrate material which is to be coated with silicon dioxide. This loading step takes place at uncritical low temperatures of about 600.degree. C. and is followed by filling the oxidation chamber with
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Bayer Thomas
Greschner Johann
Meissner Klaus
Bowers Jr. Charles L.
International Business Machines - Corporation
Soucar Steven J.
Whipple Matthew
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