Semiconductor memory device and the manufacturing method thereof

Details Semiconductor memory device and the manufacturing method thereof Semiconductor memory device and the manufacturing method thereof

1993-10-12

1995-07-25

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257904, 257758, 257401, 257903, H01L 2702, H01L 2904

Patent

active

054365066

ABSTRACT:
An SRAM memory cell structure is provided which has the access transistor gates formed from a different layer than that of the word line. The first access transistor gate of a first memory cell is connected to the first access transistor gate of an adjacent second memory cell, and a second access transistor gate of the first memory cell is connected to a second access transistor gate of an third oppositely adjacent memory cell. Each pair of coupled gates are formed separate from the access transistor gates in adjacent memory cells. The word lines connect the separated access transistor gates. The word lines are formed on an insulating layer above the gates of the access transistors. The word lines are, however, electrically connected to the gates of the access transistors through contact holes formed in the insulating layer. Each memory cell is arranged symmetrically with respect to an adjacent memory cell, and the components of each memory cell are symmetrical. Therefore, a structure and a method for a reduction in the area of an SRAM cell of the conventional circuit design is provided, resulting in a larger layout margin and a more reliable and more highly integrated SRAM device.

REFERENCES:
patent: 5005068 (1991-04-01), Iheda et al.
IBM Technical Disclosure Bulletin, vol. 33, #1B pp. 352-354 Jun. 1990 257/903.

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