Scan testable circuit arrangement

Details Scan testable circuit arrangement Scan testable circuit arrangement

1997-10-27

2000-03-21

Tu, Trinh L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

370241, 370911, G01R 3128

Patent

active

060414278

ABSTRACT:
A circuit arrangement utilizes a common bus for functional operations of logic circuits and for scan testing the logic circuits. In one embodiment, input/output ports and scan test ports of the logic circuits are switchably coupled to a bus. For functionally testing the logic circuits, a predetermined command transmitted over the bus causes the scan test ports to be coupled to the bus and the input/output ports to be decoupled from the bus. Test data may then be transmitted to and from the logic circuits via the bus. When testing is complete, a second predetermined command transmitted over the bus causes the scan test ports to be decoupled from the bus and the input/output ports to be coupled to the bus.

REFERENCES:
patent: 4357703 (1982-11-01), Brunt
patent: 4625310 (1986-11-01), Mercer
patent: 4926424 (1990-05-01), Maeno
patent: 5161160 (1992-11-01), Yaguchi et al.
patent: 5471481 (1995-11-01), Okumoto et al.

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