Method of producing and arrangement containing self-amplifying d

Details Method of producing and arrangement containing self-amplifying d Method of producing and arrangement containing self-amplifying d

1996-11-18

1998-01-20

Nguyen, Tuan H.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438270, 438237, H01L 21336

Patent

active

057100721

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates generally to a method produce an arrangement containing self-amplifying dynamic MOS transistor memory cells which each comprise a selection transistor, a memory transistor and a diode structure.
2. Description of the Related Art
With increasing storage density per chip from one memory generation to the next, the area of dynamic semiconductor memory cells is being continuously reduced. For this purpose, from the 4 Mbit memory generation onwards, three-dimensional structures are necessary. From the 64 Mbit memory generation onwards, the memory capacity has reached a value which can hardly still be reduced, with the result that an approximately constant capacity has to be formed on a reduced cell area. This results in an appreciable technological expenditure. It is therefore necessary to impose on an improved dynamic semiconductor memory cell the requirement that the level of the signal charge is not determined by the size of the memory capacity.
This requirement is fulfilled by memory cells in which the signal charge is provided not by a storage capacitor but by a supply-voltage source. In this case, it is sufficient to store in the storage capacitor only a smaller charge which, when the memory cell is read out, activates a switching element so that a conducting connection is made between the supply-voltage source and the bit line. Such memory cells are referred to as self-amplifying memory cells or gain memory cells.
The publication by T. Tsuchiya et al., IEEE Electr. Dev. Lett. (1982), EDL-3, page 7 and T. Tsuchiya et al., IEEE Trans. Electr. Dev. (1982), ED-29, page 1713, disclose a self-amplifying memory cell containing a barrier-layer field-effect transistor. In this type of memory cell, the stored charge controls the extent of a space-charge zone of a p-n junction. If the cell is charged, the space-charge zone is enlarged to such an extent that it constricts the current channel between voltage source and bit line. If, on the other hand, no charge is stored in the cell, the current channel is not constricted and current is able to flow from the voltage source to the bit line. In this type of cell, the semiconductor region forming the p-n junction and the current channel can only have low tolerances so as to ensure both adequate current flow and also reliable blocking during corresponding charging. In addition, an additional line is needed to write the information.
The publication by K. Terada et al., IEEE Trans. Electr. Dev. (1982), ED-29, page 1301, discloses a self-amplifying memory cell containing a DMOS transistor. In this case, a planar MOS transistor and a DMOS transistor are integrated with one another. The charge representing the information is stored in the substrate of the DMOS transistor. Depending on the charging state of the substrate, the DMOS transistor assumes two different threshold voltages. In this type of cell, positive and negative voltages are necessary on the word line. Furthermore, the levels must be adjusted very precisely in order to be able to differentiate between a logic "zero" and "one" during reading-out.
The publication by T. N. Blalock et al., Symp. VLSI Circuits Dig. Tech. Pap. (1990), page 13, discloses a two-transistor memory cell which has been developed from the three-transistor cell and in which the third transistor, which is used to read out, is omitted. Instead, the state of the memory transistor is scanned by lines arranged in matrix fashion. This type of cell requires four lines, which have to be routed over the cell array in the form of a double matrix. Four contacts are necessary for each cell, which limits the reduction in the cell area. Furthermore, the source and drain regions of the two transistors cannot be formed by a common doped zone, as would be necessary for a small cell area.
A self-amplifying memory cell containing an MOS transistor and a bipolar transistor is disclosed, for example, by K. Sunouchi et al., in the publication IEDM Tech. Dig. (1991), page 465. In th

REFERENCES:
patent: 4670768 (1987-06-01), Sunami et al.
patent: 4788158 (1988-11-01), Chatterjee
patent: 4989055 (1991-01-01), Redwine
patent: 4999811 (1991-03-01), Banerjee
patent: 5164325 (1992-11-01), Cogan et al.
patent: 5327374 (1994-07-01), Krautschneider et al.
patent: 5330927 (1994-07-01), Lee
patent: 5443992 (1995-08-01), Risch et al.
T. Tsuchiya et al., "New Dynamic Ram Cell for VLSI Memeroies", IEEE Electron Device Letters, vol., EDL-3, 1982, 4 pages.
T. Tscuhiya et al., "Miniaturization Degree of Dynamic MOS Ram Cells with Readout Signal Gain", IEEE Transactions on Electron Devices, Vool., Ed-29, No. 11 1982, pp. 1713-1717.
K. Terada et al., "A New VLSI Memory Cell Using DMOS Technology (DMOS Cell)", IEEE Transactions on Electron Devices, vol., ED-29, No. 8, 1982, pp. 1301-1308.
T. Blalock et al., "A Nevel 8 ns 2T Dram Cell Topology with Non-Destructive Readout Utilizing a Clamped Bit Line CMOS Sense Amplifier", Memory/Emerging Technology.
K. Sunouchi et al., "A Self-Amplifying (SEA) Cell for Future high Density Drams", IEDM Tech., Dig. 1991, pp. 17.1.1-17.1.4.
Krautschneider et al., "Fully Scalable Gain Memory Cell for Future Drams", Microelectronic Engineering, 1991, pp. 367-370.
IBM Technical Disclosure Bulletin, vol., 34, No. 6, Nov. 1991, "Common-Wordline Compact Merged Dram Cell", pp. 231-233.
Japanese Abstract, "Semiconductor Storage Device", vol. 14, No. 105, 1990 1-307256, Dec. 12, 1989.
Japanese Abstract, "Semiconductor Storage Device and Manufacture Thereof", vol. 14, No. 205, 1990, 2-44763, Feb. 14, 1990.

Affiliated with

Also associated with

Rating

Method of producing and arrangement containing self-amplifying d does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of producing and arrangement containing self-amplifying d, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of producing and arrangement containing self-amplifying d will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-724990