Data output circuit for dynamic memory device

Details Data output circuit for dynamic memory device Data output circuit for dynamic memory device

1984-05-16

1986-07-29

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365190, 365203, G11C 700

Patent

active

046034030

ABSTRACT:
Data from a latch section for latching the contents in a plurality of memory cells are selectively applied to a data output section through paired output lines. In the data output section, immediately before the data is output, the nodes providing gate inputs to a load transistor and a drive transistor are connected to a signal for driving the output section and become at ground level. The output of the data, which is the same as that produced in the previous cycle, is continued till the start of a cycle in which the data from the latch section is output to the output line pair. At the start of a cycle in which new data is applied from the output line pair, a reset operation is performed.

REFERENCES:
patent: 4397000 (1983-08-01), Nagami
Nakano et al., "A Sub 100ns 256Kb Dram," IEEE International Solid-State Circuits Conference, pp. 224-225, Feb. 25, 1983.
Moench, et al., "A Sub 100ns 256K DRAM," IEEE International Solid-State Circuits Conference, pp. 230-231, Feb. 25, 1983.

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