Spin-on-glass partial etchback planarization process

Details Spin-on-glass partial etchback planarization process Spin-on-glass partial etchback planarization process

1995-09-18

1997-09-09

Breneman, R. Bruce

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438631, 438699, H01L 21465

Patent

active

056656572

ABSTRACT:
A method for forming a planarization SOG layer which eliminates voids in SOG layers in-between closely spaced conductive lines is provided. A first dielectric layer is formed over the spaced conductive lines thus forming voids or closed cavities in the first dielectric layer between the lines. The first dielectric layer is covered with a first spin-on-glass layer. The first spin-on-glass layer is anisotropically etched to a depth which exposes the voids and forms open hollows. Subsequently, a second spin-on-glass layer is formed over the remaining first spin-on-glass layer whereby the voids or open hollows are filled with the second spin-on-glass layer. The second spin-on-glass layer is etched to expose the first dielectric layer in the via hole areas. Subsequently, a second dielectric layer is deposited over the first and second spin-on-glass layers to complete the planarization. This process fills voids formed in the first dielectric layer and forms a smoother top surface. The process forms via holes that do not adjoin the SOG layers, thereby reducing the poison via problem.

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