Read circuit for memory

Details Read circuit for memory Read circuit for memory

1997-11-14

1999-04-27

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

365206, 365207, G11C 700

Patent

active

058986227

ABSTRACT:
A memory read circuit includes an input to be connected to a bit line to which there are connected memory cells, and an output to produce an output logic potential. A current source produces a first current and a current-voltage converter produces the output logic potential. This potential represents the value of a second current obtained by the rerouting of a part of the first current towards the bit line when one of the cells is read, so that once the bit line is charged, the value of this second current is determined solely by the state of the selected cell and is independent of the equivalent capacitive load of the bit line.

REFERENCES:
patent: 5163022 (1992-11-01), Homma et al.
patent: 5199000 (1993-03-01), Takahashi
patent: 5373469 (1994-12-01), Akioka et al.
patent: 5563826 (1996-10-01), Pascucci et al.
patent: 5734616 (1998-03-01), Kazama et al.
Izumikawa et al., IEICE Trans. Electron., vol. E79, No. 7, (Jul. 7, 1996), pp. 957-962, "A Current Direction Sense Technique for Multiport SRAM's".
Watanbe et al., IEEE Journal of Solid-State Circuits, vol. 29, No. 1, (Jan. 29, 1994), pp. 9-13, "Offset Compensating Bit-Line Sensing Scheme for High Density DRAM'".

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