Slew rate limited output driver

Details Slew rate limited output driver Slew rate limited output driver

1997-10-16

2000-02-29

Tokar, Michael

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

326 83, 326 88, H03K 1716

Patent

active

060313897

ABSTRACT:
A slew-rate limited output driver circuit that minimizes switching current while delivering sufficient peak load currents is disclosed. The circuit of the present invention includes fixed pull-up and pull-down transistors that are designed to dissipate minimum switching current while maintaining a predetermined slew rate. Additional pull-up and pull-down transistors are then switched in parallel to the fixed pull-up and pull-down transistors to drive the output all the way to full logic levels, after the output signal has made most of its transition. In a preferred embodiment, each switched transistor is controlled by a comparator that generates its output by comparing the level of the output signal to a predetermined reference voltage.

REFERENCES:
patent: 5087834 (1992-02-01), Tsay
patent: 5134311 (1992-07-01), Biber et al.
patent: 5488322 (1996-01-01), Kaplinsky
patent: 5598119 (1997-01-01), Thayer et al.
patent: 5748019 (1998-05-01), Wong et al.
patent: 5777944 (1998-07-01), Knaack et al.

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