Method of manufacturing a semiconductor device having various ty

Details Method of manufacturing a semiconductor device having various ty Method of manufacturing a semiconductor device having various ty

1995-09-07

1999-04-27

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438258, H01L 21336, H01L 218234

Patent

active

058980067

ABSTRACT:
In a method of manufacturing a semiconductor device including a first MOSFET for a non-volatile memory element, a second MOSFET for an input protecting element and a third MOSFET for a logic circuit element, gate structures of the first to third MOSFETs are formed on a p-type substrate. Then, an n-type impurity is injected in the substrate in self-alignment with the gate structure for the third MOSFET with a first dose amount to form source and drain regions for the third MOSFET. An n-type impurity is simultaneously injected in the substrate in self-alignment with the gate structures for the first and second MOSFETs to form source and drain regions for the first and second MOSFETs. A side wall insulating film is formed on a side wall of each of the gate structures of the thirst to third MOSFETs. An n-type impurity is injected in parts of the source and drain regions of the third MOSFET in self-alignment with the side wall and gate structure with a second dose amount which is higher than the first dose amount.

REFERENCES:
patent: 4745083 (1988-05-01), Huie
patent: 4775642 (1988-10-01), Chang et al.
patent: 4851361 (1989-07-01), Schumann et al.
patent: 5098855 (1992-03-01), Komori et al.
patent: 5183773 (1993-02-01), Miyata

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