Method for forming dual-gate CMOS for dynamic random access memo

Details Method for forming dual-gate CMOS for dynamic random access memo Method for forming dual-gate CMOS for dynamic random access memo

1997-12-30

2000-02-29

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

H01L 218238

Patent

active

060308613

ABSTRACT:
A method for forming a dual-gate transistor includes the step of forming a gate oxide layer (18) over two transistor regions provided by a P-tank (12) and an N-tank (14). This is followed by depositing a layer of in-situ doped poly (20) and then masking off a portion of the poly layer (20) overlying the P-tank (12). This is then followed by diffusion of P-type impurities into the portion of the poly layer (20) overlying the N-tank (14) associated with the P-channel transistor. This is a process required for forming a DRAM memory. Utilizing the same oxide mask (22), a threshold implant is formed into the N-type (14).

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patent: 5384724 (1995-01-01), Jagini
patent: 5550079 (1996-08-01), Lin
patent: 5563093 (1996-10-01), Koda et al.
patent: 5747368 (1998-05-01), Yang et al.
patent: 5851865 (1998-12-01), Koike

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