Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Precharge

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365189, 365206, 365230, G11C 1140

Patent

active

048212342

ABSTRACT:
When a pair of word lines 1 and 2 change from a selected state to a non selected state, a word line discharging circuit 10 enables a transistor 15 to conduct during a period when this pair of word lines 1 and 2 are maintained at the highest potential compared with the other pairs of word lines, so that the pair of word lines 1 and 2 are discharged by means of a first discharging current source 11. The word line discharging circuit 10 enables a transistor 16 to conduct after another pair of word lines attain the highest potential, so that the pair of word lines 1 and 2 are discharged by means of a second discharging current source 12.

REFERENCES:
patent: 4393476 (1983-07-01), Ong
ISSCC, Feb. 24, 1983, "A 15ns 16Kb ECL RAM with a PNP Load Cell", by Kazuhiro Toyoda et al.
ISSCC, Feb. 20, 1986, "A 3.5ns, 2W, 20mm.sup.2 16Kb ECL Bipolar RAM", by Kunihiko Yamaguchi et al.

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