Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

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365190, G11C 1140

Patent

active

045584346

ABSTRACT:
A semiconductor memory device having matrix-arranged memory cells, carrying out data write or read operations to or from a selected memory cell through a pair of data buses by the selection of a word line and a pair of bit lines, includes two transfer devices which transfer data between bit lines and data buses and which are separately operated for either writing or reading. Even if a data read operation is stopped midway by a system reset or the like, the stored data in the memory cell is not destroyed.

REFERENCES:
patent: 4379342 (1983-04-01), Nakano et al.

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