Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1997-08-26
2000-01-18
Chung, Phung M.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714724, H04B 1700
Patent
active
060165642
ABSTRACT:
The invention provides a method of design for testability of a fault in a portion difficult to test such as an enable input of a tristate element. With regard to an integrated circuit design by a scan path method, an observation circuit including an EXOR tree having inputs in the number equal to that of tristate elements to be designed for testability and an observation dedicated scan FF is disposed. The enable inputs of the tristate elements are connected with the input terminals of the EXOR tree, and the output terminal of the EXOR tree is connected with the ordinary data input terminal of the observation dedicated scan FF. Furthermore, the observation scan FF is inserted into a scan chain already formed by the scan path method. In this manner, a fault in logic circuits for controlling the enable input of the tristate elements, which are conventionally difficult to be detected, can be observed at an external output pin through the scan chain.
REFERENCES:
patent: 5329533 (1994-07-01), Lin
patent: 5515517 (1996-05-01), Nozuyama et al.
patent: 5646422 (1997-07-01), Hashizume
Chung Phung M.
Matsushita Electric - Industrial Co., Ltd.
LandOfFree
Method of design for testability, method of design for avoiding does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of design for testability, method of design for avoiding , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of design for testability, method of design for avoiding will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-570713