Failure analysis method and device

Details Failure analysis method and device Failure analysis method and device

1998-04-07

2000-01-18

Nelms, David

Static information storage and retrieval

Read/write circuit

Bad bit

36446817, 365201, G11C 700

Patent

active

060162783

ABSTRACT:
A method comprises steps of: forming a FBM (step S1); generating a second failure map by compressing data of the FBM (step S2); recognizing a failure mode from the second failure map (step S3); selecting a specific failure mode (step S4); and analyzing the specific failure mode by using a part of the corresponding FBM (step S5). This makes a detail analysis possible while suppressing the number of processing data, and thereby achieves a failure analysis method and device improving accuracy and reliability in comparison result.

REFERENCES:
patent: 5844850 (1998-12-01), Tsutsui et al.
H. Nakawatase, et al., Expert System for Semiconductor Failure Analysis Using ARES.TM./DIAG, Toshiba Review, vol. 49, No. 8, 1994, pp. 563-566.

Affiliated with

Also associated with

Rating

Failure analysis method and device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Failure analysis method and device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Failure analysis method and device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-567403