Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1998-05-04
2000-01-18
Booth, Richard
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438629, 438644, 438654, 438660, 438663, 438687, H01L 214763
Patent
active
060157496
ABSTRACT:
A method for fabricating a copper interconnect structure, using a Cu.sub.3 Ge intermetallic layer, as an adhesive layer, has been developed. Following the deposition of a copper seed layer, an ion implantation procedure is performed, placing germanium ions in a copper seed layer. After deposition of a thick copper layer, an anneal cycle, performed before or after deposition of the thick copper layer, is used to create a Cu.sub.3 Ge intermetallic layer at the interface between a copper seed layer and a titanium nitride barrier layer. A second embodiment of this invention uses a tilted, germanium ion implantation procedure, used to avoid the placement of germanium ions in a copper seed layer, at the bottom of a contact hole, thus avoiding possible implantation damage, to active device regions, exposed in the bottom of the contact hole.
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Chen Lih-Juann
Lai Jane-Bai
Liu Chung-Shi
Yu Chen-Hua Douglas
Ackerman Stephen B.
Booth Richard
Saile George O.
Taiwan Semiconductor Manufacturing Company
Zarneke David A
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