Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1994-08-02
2000-07-11
Zarabian, A.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365207, 365208, G11C 700
Patent
active
060882700
ABSTRACT:
A sense amplifier for a very high density integrated circuit memory using CMOS technology is described. Each sense amplifier includes first and second local sense amplifier drive transistors, one connecting the P channel transistors to VCC; the other connecting the N channel transistors to VSS. A read amplifier circuit is provided within each sense amplifier and is operated by read control signals. Internal nodes of the latch of the sense amplifier are coupled by pass transistors that are responsive to column write control signals. Local data write driver transistors are also provided to selectively couple the pass transistors to VCC-Vt or VSS in response to further data write control signals. A relatively wider power line is coupled to the drive transistors to provide VCC thereto, and a narrower line is used to control those first sense amplifier drive transistors. Corresponding wide and narrow lines are used for the second local sense amplifier drive transistors which couple the N channel transistors to ground. Each sense amplifier may be shared between first and second pairs of bit lines through the use of isolation transistors and a corresponding isolation signal.
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English abstract re JP 2-18785 to Hitachi Ltd.
English abstract re JP 4-228171 to Hitachi Ltd.
English abstract re JP 4-252493 to NEC Corp.
English abstract re JP 5-303495 to Yamatake Honeywell Co., Ltd.
Nippon Steel Semiconductor Corporation
United Memories Inc.
Zarabian A.
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