Semiconductor memory device and fabrication method thereof

Details Semiconductor memory device and fabrication method thereof Semiconductor memory device and fabrication method thereof

1998-06-05

2000-07-11

Whitehead, Jr., Carl

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257308, 257309, 438255, 438398, H01L 27108

Patent

active

060876948

ABSTRACT:
A capacitor lower electrode is formed so as to be connected to a main surface of a silicon substrate. The capacitor lower electrode includes a plug portion, a bottom wall portion, and a vertical wall portion. An insulation layer for suppressing crystallization of the vertical wall portion is formed between the bottom wall portion and the vertical wall portion. A capacitor upper electrode is formed on the capacitor lower electrode with a capacitor dielectric layer therebetween.

REFERENCES:
patent: 5290729 (1994-03-01), Hayashide et al.
patent: 5366917 (1994-11-01), Watanabe et al.
patent: 5597760 (1997-01-01), Hirota
patent: 5623243 (1997-04-01), Watanabe et al.
patent: 5843829 (1998-12-01), Kuramae et al.

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