Method of fabricating a semiconductor memory having an address d

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438128, 438129, H01L 218242

Patent

active

057338078

ABSTRACT:
The invention provides a semiconductor memory including an address decoder, a first word line in electrical connection with an output terminal of the address decoder, a plurality of second word lines, a plurality of memory cells in electrical connection in parallel with each of the second word lines, a plurality of contacts each of which electrically connects each of the second word line to the first word line, and a compensator for signal delay among the memory cells in each of the second word lines. In accordance with the semiconductor memory, a group of the second word lines are connected to the first word line through a contact. Thus, since it is impossible for a memory cell in connection with the first word line through a defective contact to carry out writing data therein and reading data therefrom, such a memory cell can be readily, electrically found for removal.

REFERENCES:
patent: 5457648 (1995-10-01), Eisig
patent: 5463577 (1995-10-01), Oowaki et al.
patent: 5497353 (1996-03-01), Sato et al.
patent: 5528545 (1996-06-01), Takahashi et al.

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