Transistors having controlled conductive spacers, uses of such t

Details Transistors having controlled conductive spacers, uses of such t Transistors having controlled conductive spacers, uses of such t

1997-12-10

1999-12-21

Munson, Gene M.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257296, 257344, 257 42, H01L 2978, H01L 27108

Patent

active

060052732

ABSTRACT:
A transistor structure includes an insulated conductive gate spacer or a conductive layer under a nonconductive spacer, together forming a composite spacer, which contacted and driven separately from the conventional gate of the transistor. The gate spacer, conductive layer of a composite spacer or a portion or portions thereof serve as a control or controls for the transistors taking the form of a second gate or second and third gates for the transistors. The transistors may be used throughout an integrated circuit or it may be preferred to use the improved transistor only in critical speed paths of an integrated circuit. Delays within circuits including the improved transistors are reduced since the drain voltage can be higher than VCC and the BVDSS and subthreshold voltage are substantially higher than standard LDD transistors. When the improved transistors are used selectively within an integrated circuit, the remaining devices can be structured as standard LDD transistors, using the gate spacers in a conventional manner, and/or as conventional transistors.

REFERENCES:
Tiao-yuan Huang, William W. Yao, Russell A. Martin, Alan G. Lewis, Mitsumasa Koyanagi, & John Y. Chen, A Novel Submicron LDD Transistor with Inverse-T Gate Structure, IDEM 1986, pp. 742-745.
I. C. Chen, J. P. Lin, and C. W. Teng, Article from 1990 Symposium on VLSI Technology entitled: "A Highly Reliable 0.3 .mu.m N-channel MOSFET Using Poly Spacers", pp. 39-40.
Masataka Minami, Yasuo Sawahata, Hiroshi Matsuki and Takahiro Nagano, Article from 1990 Symposium on VLSI Technology entitled: A High Speed & High Reality MOFSET Utilizing an Auxiliary Gate, pp. 41-42.
F.-C. Hsu and K.-Y. Chiu, Article from IEEE Electron Device Letters, vol. EDL-5, No. 5, entitled: Evaluation of LDD MOSFET's Based on Hot-Electron-Induced Degradation, May 1984, pp. 162-165.

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