Method to fabricate embedded DRAM

Details Method to fabricate embedded DRAM Method to fabricate embedded DRAM

1998-12-22

2000-10-17

Elms, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438241, H01L 218234, H01L 218244

Patent

active

061330833

ABSTRACT:
A method for fabricating an embedded DRAM. A substrate having a memory circuit region and a logic circuit region is provided. A first gate, a first source/drain region and a second source/drain region are formed in the memory circuit region. A second gate and a third source/drain region are formed in the logic circuit region. A first dielectric layer is formed over the substrate. In the first dielectric layer, a first contact hole is formed to expose the first source/drain region and a second contact hole is formed to expose the second gate and the third source/drain region. A bit line is formed to electrically couple with the first source/drain region through the first contact hole. A local interconnect is formed to electrically couple with the second gate and the third source/drain region through the second contact hole. A second dielectric layer is formed over the substrate. A third contact hole is formed in the first dielectric layer and the second dielectric layer to expose the second source/drain region. A capacitor is formed to electrically couple with the second source/drain region through the third contact hole.

REFERENCES:
patent: 4985718 (1991-01-01), Ishijima
patent: 5661063 (1997-08-01), Lee

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