Trench DRAM cell with dynamic gain

Details Trench DRAM cell with dynamic gain Trench DRAM cell with dynamic gain

1987-11-30

1991-03-12

Gossage, Glenn

Static information storage and retrieval

Systems using particular element

Capacitors

357 236, 365 51, G11C 1124

Patent

active

049998110

ABSTRACT:
A two transistor gain-type dynamic random access memory (DRAM) cell (8) formed in a trench (30) to optimize wafer area requirements. Formed on a heavily doped semiconductor substrate (20) are alternate layers of P-type and N-type semiconductor material defining the elements of a vertical pass transistor (12) and gain transistor (24). A trench is formed through the alternate semiconductor layers into the substrate (20), and filled with two regions of a semiconductor material defining a storage node (18) and, insulated therefrom, a word line (16). The gain transistor (24) is fabricated having a response time faster than that of the pass transistor (12) so that, during read operations, the gain transistor (24) changes the precharged voltage of the read bit line (26), depending upon the charge stored in the capacitor storage node (18).

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patent: 4704705 (1987-11-01), Womack
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patent: 4763181 (1988-08-01), Tasch, Jr.
patent: 4845539 (1989-07-01), Inoue
patent: 4864374 (1989-09-01), Banerjee
Shichijo et al, "TITE RAM: A New SOI DRAM Gain Cell for Mbit DRAM's", Extended Abstracts of the 16th (1984 International) Conference on Solid State Devices and Materials, Kobe, 1984, pp. 265-268.

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