Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1995-06-06

1997-03-11

Jackson, Jr., Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257296, 257300, 257303, 257304, 257305, 257311, H01L 27108, H01L 2976, H01L 2994, H01L 31119

Patent

active

056104189

ABSTRACT:
A highly integrated semiconductor memory device having large storage capacity is obtained in which dimension loss of a storage node of a capacitive element of a memory cell from the design can be suppressed and desired capacitance value is ensured. A storage node of the capacitive element of each memory cell is formed by a third conductive layer positioned above a second conductive layer serving as the bit line, on one major surface of semiconductor substrate. Storage node is electrically connected to one of source/drain regions of the transistor element of the corresponding memory cell. The storage node is arranged between a word line to which the corresponding memory cell is connected, and another word line adjacent to said word line on the side source/drain region of the transistor element of the corresponding memory cell, and crossing a bit line which is connected to the corresponding memory cell.

REFERENCES:
patent: 5138412 (1992-08-01), Hieda et al.
patent: 5235199 (1993-08-01), Hamamoto et al.
patent: 5363326 (1994-11-01), Nakajima
patent: 5373177 (1994-12-01), Kitaoka
"A 1.28 .mu.m 2 Bit-Line Shielded Memory Cell Technology for 64 Mb DRAMs", by Y. Kawamoto et al., 1990 Symposium on VLSI Technology, pp. 13-14.
"Fabrication of Storage Capacitance-Enhanced Capacitors with a Rough Electrode", by Yoshio Hayashide et al., Japanese Journal of Applied Physics, vol. 29, 1990, pp. L2345-L2348.
"State of Art DRAM Processing Technique", Mitsubishi Electric Technical Report, vol. 63, No. 11, 1989, pp. 17-22.

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