Planarization method for a semiconductor substrate

Details Planarization method for a semiconductor substrate Planarization method for a semiconductor substrate

1992-04-30

1994-03-22

Hearn, Brian E.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156653, 156656, 156657, 1566591, 437228, 437229, 437231, 437978, H01L 21306

Patent

active

052960927

ABSTRACT:
Disclosed is a method for planarizing the insulating layer formed on a semiconductor substrate without forming voids. An insulating layer is coated on a semiconductor substrate on which a metal wiring layer has been previously formed, and then a resist layer serving as a sacrificial layer is formed on the insulating layer. Etching the sacrificial layer provides a sacrificial residue on the insulating layer between portions of the metal wiring layer. After an upper portion of the insulating layer is istropically etched, the insulating layer and sacrificial residue are anisotropically etched. An insulating layer thus-obtained has a good profile so that a planarized insulating interlayer free of voids is obtained by an additional etch-back process using a second sacrificial layer. Consequently, a subsequent second metal wiring formation or lithography process can be easily carried out.

REFERENCES:
patent: 4952274 (1990-08-01), Abraham
patent: 5006485 (1991-04-01), Villalon
patent: 5139608 (1992-08-01), Grivna
Translation of Shimizu JP 1-094623.
Wolf, Silicon Processing for the VLSI Era, vol. 2, Lattice Press, Sunset Beach, (1990) pp. 222-235.
L. Molnar et al., "SOG Planarization Proves Better than Photoresist Etch Back," Semiconductor International, Aug. 1989, pp. 92-96.

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