Method of manufacturing devices having vertical junction edge

Details Method of manufacturing devices having vertical junction edge Method of manufacturing devices having vertical junction edge

2006-05-24

2011-12-27

Lee, Eugene (Department: 2815)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S241000, C438S242000, C438S243000

Reexamination Certificate

active

08084322

ABSTRACT:
Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a doped polysilicon. Vertical junctions are formed between the polysilicon and the exposed substrate at the trench edges such that during a thermal cycle, the doped polysilicon will out-diffuse doping elements into the adjacent single crystal silicon advantageously forming a diode extension having desirable properties.

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