Protecting data on integrated circuit

Details Protecting data on integrated circuit Protecting data on integrated circuit

2008-10-28

2011-12-06

Trimmings, John (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S727000, C714S724000, C714S733000, C714S734000, C326S008000, C326S016000, C713S182000, C713S193000, C713S194000, C711S100000, C726S026000, C726S027000, C726S011000, C726S017000, C726S021000

Reexamination Certificate

active

08074132

ABSTRACT:
Various example embodiments are disclosed. According to one example embodiment, an integrated circuit may include a mode block, a plurality of data blocks, and a reset node. The mode block may be configured to output a test mode signal, a scan mode signal, and a trigger signal based on a received data input. The plurality of data blocks may each include registers configured to store data, each of the plurality of data blocks being configured to write over at least some of the data stored in their respective registers in response to receiving a write-over instruction. The reset node may be configured to reset the registers based on receiving either a first reset input or a second reset input. The integrated circuit may be configured to enter a test mode, enter a scan mode, and exit the test mode.

REFERENCES:
patent: 7363564 (2008-04-01), Moss et al.
patent: 7487418 (2009-02-01), Kayukawa et al.
patent: 2007/0226562 (2007-09-01), Tkacik et al.
patent: 2008/0010570 (2008-01-01), Yamazaki
“IEEE Std 1149.1 (JTAG) Testability”, Texas Instruments, Primer 1997 130 pages.
“JTAG (IEEE 1149.1/P1149.4) Tutorial Introductory”, TI Test Symposium 1997 , 7 pages.

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