Data output circuit in a semiconductor memory apparatus

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

Reexamination Certificate

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Details

C365S189080, C365S194000, C365S230060, C327S396000, C327S393000, C327S100000, C327S404000

Reexamination Certificate

active

08045399

ABSTRACT:
A data output circuit in a semiconductor memory apparatus includes a pre-driver configured to receive input data and then produce a pull-up signal and a pull-down signal, a pull-up driver configured to pull-up drive a first node in response to the pull-up signal and provide an additional pull-up drive when a voltage level on the first node transitions, a pull-down driver configured to pull-down drive a second node in response to the pull-down signal and provide an additional pull-down drive when a voltage level on the second node transitions, and a pad coupled to the first and second nodes to generate output data.

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patent: 6094086 (2000-07-01), Chow
patent: 6130563 (2000-10-01), Pilling et al.
patent: 7279933 (2007-10-01), Lee
patent: 7282968 (2007-10-01), Lee
patent: 2004/0251940 (2004-12-01), Hayashi et al.
patent: 2005/0083766 (2005-04-01), Kim et al.
patent: 2007/0182453 (2007-08-01), Lee
patent: 2008/0088365 (2008-04-01), Jang
patent: 2004-327602 (2004-11-01), None
patent: 1020070070989 (2007-07-01), None

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