Multi-bit memory error detection and correction system and...

Details Multi-bit memory error detection and correction system and... Multi-bit memory error detection and correction system and...

2007-03-30

2011-11-08

Lamarre, Guy (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

C365S185030

Reexamination Certificate

active

08055988

ABSTRACT:
A system and method for operating a collection of memory cells includes storing binary data values and parity data values by associating binary values with a common adjustable characteristic parameter of a memory cell collection. Probability distribution functions for values of the characteristic parameter of the memory cell collection are read and constructed. Binary data values and parity data values stored in the memory cell collection are retrieved. Parity data for error detection and error correction is evaluated in the binary data values.

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LAM; Maximum Likelihood Statistical Method of Operations for Multi-Bit Semiconductor Memory; Unpublished U.S. Appl. No. 11/620,704, filed Jan. 7, 2007.

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