Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2010-03-25
2011-11-08
Lee, Eugene (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S345000, C257S335000, C257SE29117
Reexamination Certificate
active
08053839
ABSTRACT:
A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.
REFERENCES:
patent: 4933298 (1990-06-01), Hasegawa
patent: 4946799 (1990-08-01), Blake et al.
patent: 5115289 (1992-05-01), Hisamoto et al.
patent: 5317175 (1994-05-01), Throngnumchai
patent: 5317178 (1994-05-01), Wu
patent: 5464783 (1995-11-01), Kim et al.
patent: 5607865 (1997-03-01), Choi et al.
patent: 5801397 (1998-09-01), Cunningham
patent: 5814895 (1998-09-01), Hirayama
patent: 5998852 (1999-12-01), Berry et al.
patent: 6114725 (2000-09-01), Furukawa et al.
patent: 6157061 (2000-12-01), Kawata
patent: 6222234 (2001-04-01), Imai
patent: 6252284 (2001-06-01), Muller et al.
patent: 6300182 (2001-10-01), Yu
patent: 6342410 (2002-01-01), Yu
patent: 6344392 (2002-02-01), Liaw
patent: 6380024 (2002-04-01), Liaw
patent: 6387739 (2002-05-01), Smith, III
patent: 6391695 (2002-05-01), Yu
patent: 6391782 (2002-05-01), Yu
patent: 6391796 (2002-05-01), Akiyama et al.
patent: 6411725 (2002-06-01), Rhoads
patent: 6413802 (2002-07-01), Hu et al.
patent: 6432829 (2002-08-01), Muller et al.
patent: 6451656 (2002-09-01), Yu et al.
patent: 6475869 (2002-11-01), Yu
patent: 6475890 (2002-11-01), Yu
patent: 6476437 (2002-11-01), Liaw
patent: 6492212 (2002-12-01), Ieong et al.
patent: 6514808 (2003-02-01), Samavedam et al.
patent: 6521949 (2003-02-01), Assaderaghi et al.
patent: 6525403 (2003-02-01), Inaba et al.
patent: 6534807 (2003-03-01), Mandelman et al.
patent: 6562491 (2003-05-01), Jeon
patent: 6573549 (2003-06-01), Deng et al.
patent: 6596599 (2003-07-01), Guo
patent: 6605514 (2003-08-01), Tabery et al.
patent: 6610576 (2003-08-01), Nowak
patent: 6611029 (2003-08-01), Ahmed et al.
patent: 6617210 (2003-09-01), Chau et al.
patent: 6635909 (2003-10-01), Clark et al.
patent: 6642090 (2003-11-01), Fried et al.
patent: 6657252 (2003-12-01), Fried et al.
patent: 6686231 (2004-02-01), Ahmed et al.
patent: 6706571 (2004-03-01), Yu et al.
patent: 6720231 (2004-04-01), Fried et al.
patent: 6720619 (2004-04-01), Chen et al.
patent: 6762448 (2004-07-01), Lin et al.
patent: 6768158 (2004-07-01), Lee et al.
patent: 6787854 (2004-09-01), Yang et al.
patent: 6821834 (2004-11-01), Ando
patent: 6833588 (2004-12-01), Yu et al.
patent: 6844238 (2005-01-01), Yeo et al.
patent: 6855606 (2005-02-01), Chen et al.
patent: 6855990 (2005-02-01), Yeo et al.
patent: 6858478 (2005-02-01), Chau et al.
patent: 6864519 (2005-03-01), Yeo et al.
patent: 6885055 (2005-04-01), Lee
patent: 6992354 (2006-01-01), Nowak et al.
patent: 7005330 (2006-02-01), Yeo et al.
patent: 7074656 (2006-07-01), Yeo et al.
patent: 7105894 (2006-09-01), Yeo et al.
patent: 7115947 (2006-10-01), Clark et al.
patent: 7148526 (2006-12-01), An et al.
patent: 7154118 (2006-12-01), Lindert et al.
patent: 7214991 (2007-05-01), Yeo et al.
patent: 7265417 (2007-09-01), Adkisson et al.
patent: 7276763 (2007-10-01), Yeo et al.
patent: 7701008 (2010-04-01), Yeo et al.
patent: 2002/0011612 (2002-01-01), Hieda
patent: 2003/0011080 (2003-01-01), Deshpande et al.
patent: 2003/0042528 (2003-03-01), Forbes
patent: 2003/0042531 (2003-03-01), Lee et al.
patent: 2003/0057486 (2003-03-01), Gambino et al.
patent: 2003/0067017 (2003-04-01), Ieong et al.
patent: 2003/0102497 (2003-06-01), Fried et al.
patent: 2003/0111678 (2003-06-01), Columbo et al.
patent: 2003/0113970 (2003-06-01), Fried et al.
patent: 2003/0178670 (2003-09-01), Fried et al.
patent: 2003/0178677 (2003-09-01), Clark et al.
patent: 2004/0007715 (2004-01-01), Webb et al.
patent: 2004/0031979 (2004-02-01), Lochtefeld et al.
patent: 2004/0036126 (2004-02-01), Chau et al.
patent: 2004/0038464 (2004-02-01), Fried et al.
patent: 2004/0061178 (2004-04-01), Lin et al.
patent: 2004/0075122 (2004-04-01), Lin et al.
patent: 2004/0087094 (2004-05-01), Wristers et al.
patent: 2004/0108523 (2004-06-01), Chen et al.
patent: 2004/0119100 (2004-06-01), Nowak et al.
patent: 2004/0145000 (2004-07-01), An et al.
patent: 2005/0121706 (2005-06-01), Chen et al.
patent: 2005/0275010 (2005-12-01), Chen et al.
patent: 2006/0234431 (2006-10-01), Yeo et al.
patent: 2617642 (1989-01-01), None
patent: 2015675 (1990-01-01), None
Chau, R., et al., “Advanced Depleted-Substrate Transistors: Single-gate, Double-gate and tri-gate,” Extended Abstracts of the 2002 International Conference on Solid State Devices and Materials (2002) pp. 68-69.
Colinge, J.P., et al., “Silicon-on-Insulator Gate—All Around Device,” International Electron Devices Meeting (Apr. 1990) pp. 595-598.
Huang, X., et al., “Sub-50 nm P-Channel FinFET,” IEEE Transactions on Electron Devices, vol. 48, No. 5 (May 2001) pp. 880-886.
Leobandung, E., et al., “Wire-Channel and Wrap-Around-Gate Metal Oxide-Semiconductor Field-Effect Transistors with a Significant Reduction of Short Channel Effects,” Journal of Vacuum Science and Technology B, vol. 15, No. 6 (Nov. 1997) pp. 2791-2794.
Wong, H.S.P., “Beyond the Conventional Transistor,” IBM Journal of Research and Development, vol. 46, No. 2/3 (Mar./May 2002) pp. 133-167.
Yang, F-L., et al., “25nm CMOS Omega FETs,” International Electron Devices Meeting, Digest of Technical Papers (Dec. 2002), pp. 255-258.
Yang, F-L., et al., “35nm CMOS FinFETs,” 2002 Symposium on VLSI Technology Digest of Technical Papers (Jun. 2002) pp. 104-105.
Auth, C. P., et al., “Scaling Theory for Cylindrical, Fully-Depleted, Surrounding-Gate MOSFET's,” IEEE Electron Device Letters, vol. 18, No. 2 (Feb. 1997) pp. 74-76.
Celik, M., et al., “A 45nm Gate Length High Performance SOI Transistor for 100nm CMOS Technology Applications,” Symposium on VLSI Technology Digest of Technical Papers (2002) pp. 166-167.
Chau, R., et al., “A 50nm Depleted-Substrate CMOS Transistor (DST),” IEDM (2001) pp. 621-624.
Chen, W., et al., “Suppression of the SOI Floating-body Effects by Linked-body Device Structure,” Symposium on VLSI Technology Digest of Technical Papers (1996) pp. 92-93.
Fung, S. K. H., et al., “Gate Length Scaling Accelerated to 30nm regime using Ultra-thin Film PD-SOI Technology,” IEDM (2001) pp. 629-632.
Geppert, L., “The Amazing Vanishing Transistor Act,” IEEE Spectrum (Oct. 2002) pp. 28-33.
Kranti, A., et al., “Design Guidelines of Vertical Surrounding Gate (VSG) MOSFETs for Future ULSI Circuit Applications,” IEEE (2001) pp. 161-165.
Je, M., et al., “Quantized Conductance of a Gate-All-Around Silicon Quantum Wire Transistor,” Microprocesses and Nanotechnology Conference (1998) pp. 150-151.
Nemati, F. et al., “A Novel Thyristor-based SRAM Cell (T-RAM) for High-Speed, Low-Voltage, Giga-scale Memories,” IEDM (1999) pp. 283-286.
Nitayama, A., et al., “Multi-Pillar Surrounding Gate Transistor (M-SGT) for Compact and High-Speed Circuits,” IEEE Transactions on Electron Devices, vol. 38, No. 3 (Mar. 1991) pp. 579-583.
Oh, Sang-Hyun, et al., “Analytic Description of Short-Channel Effects in Fully-Depleted Double-Gate and Cylindrical, Surrounding-Gate MOSFETs,” IEEE Electron Device Letters, vol. 21, No. 9 (Sep. 2000) pp. 445-447.
Sato, N., et al., “Hydrogen Annealed Silicon-On-Insulator,” Appl. Physics Letter, vol. 65, No. 15 (Oct. 10, 1994) pp. 1924-1926.
Shahidi, G.G., “SOI Technology for the GHz Era,” IBM J. Res. & Dev., vol. 46, No. 2/3 (Mar./May 2002) pp. 121-131.
Tang, S. H., et al., “F
Chen Hao-Yu
Hu Chenming
Wang Ping-Wei
Yang Fu-Liang
Yeo Yee-Chia
Lee Eugene
Slater & Matsil L.L.P.
Taiwan Semiconductor Manufacturing Company , Ltd.
LandOfFree
Doping of semiconductor fin devices does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Doping of semiconductor fin devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Doping of semiconductor fin devices will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4291541