Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2010-03-02
2011-11-01
Malsawma, Lex (Department: 2892)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S365000, C257SE21423
Reexamination Certificate
active
08048741
ABSTRACT:
A semiconductor memory device includes: a semiconductor substrate, on which an impurity diffusion layer is formed in a cell array area; a gate wiring stack body formed on the cell array area, in which multiple gate wirings are stacked and separated from each other with insulating films; a gate insulating film formed on the side surface of the gate wiring stack body, in which an insulating charge storage layer is contained; pillar-shaped semiconductor layers arranged along the gate wiring stack body, one side surfaces of which are opposed to the gate wiring stack body via the gate insulating film, each pillar-shaped semiconductor layer having the same conductivity type as the impurity diffusion layer; and data lines formed to be in contact with the upper surfaces of the pillar-shaped semiconductor layers and intersect the gate wirings.
REFERENCES:
patent: 4665418 (1987-05-01), Mizutani
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patent: 7-235649 (1995-09-01), None
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patent: 2005-85938 (2005-03-01), None
Office Action issued Dec. 14, 2010, in Japan Patent Application No. 2005-379017 (with English translation).
Arai Fumitaka
Mizukami Makoto
Shirota Riichiro
Kabushiki Kaisha Toshiba
Malsawma Lex
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
Warrior Tanika
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