Low read current architecture for memory

Details Low read current architecture for memory Low read current architecture for memory

2010-04-19

2011-10-04

Ho, Hoai v (Department: 2827)

Static information storage and retrieval

Read/write circuit

Precharge

C365S148000, C365S230030

Reexamination Certificate

active

08031545

ABSTRACT:
A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.

REFERENCES:
patent: 7701791 (2010-04-01), Rinerson et al.

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