Transistor formation using capping layer

Details Transistor formation using capping layer Transistor formation using capping layer

2010-01-12

2011-10-04

Lindsay, Jr., Walter L (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S585000, C438S591000, C257SE21444, C257SE21431

Reexamination Certificate

active

08030196

ABSTRACT:
A method of transistor formation using a capping layer in complimentary metal-oxide semiconductor (CMOS) structures is provided, the method including: depositing a conductive layer over an n-type field effect transistor (nFET) and over a p-type field effect transistor (pFET); depositing a capping layer directly over the conductive layer; etching the capping and conductive layers to form a capped gate conductor to gates of the nFET and pFET, respectively; ion-implanting the nFET transistor with a first dopant; and ion-implanting the pFET transistor with a second dopant, wherein ion-implanting a transistor substantially dopes its source and drain regions, but not its gate region.

REFERENCES:
patent: 6593198 (2003-07-01), Segawa
patent: 2006/0099748 (2006-05-01), Satou
patent: 2008/0173946 (2008-07-01), Zhu et al.
patent: 2009/0302348 (2009-12-01), Adam et al.
patent: 10-0613279 (2006-08-01), None

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