Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2008-12-17
2011-10-04
Auduong, Gene N. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S225700
Reexamination Certificate
active
08031544
ABSTRACT:
A nonvolatile memory device includes a three-dimensional (3D) cell array, a column selection circuit and a fuse block. The 3D cell array includes multiple cell arrays located in corresponding stacked substrate layers, the cell arrays sharing a bit line. The column selection circuit selects a memory unit included in the 3D cell array. The fuse block controls the column selection circuit to repair defective columns with one of multiple redundant bit lines located in the 3D cell array.
REFERENCES:
patent: 5835396 (1998-11-01), Zhang
patent: 6034882 (2000-03-01), Johnson et al.
patent: 7002825 (2006-02-01), Scheuerlein
patent: 7342843 (2008-03-01), Takeuchi et al.
patent: 7589552 (2009-09-01), Guzman et al.
patent: 7590015 (2009-09-01), Kodaira et al.
patent: 2002/0054529 (2002-05-01), Nishino et al.
patent: 2006/0221728 (2006-10-01), Fasoli et al.
patent: 2008/0198646 (2008-08-01), Park et al.
patent: 1020060019947 (2006-06-01), None
patent: 1020070036550 (2007-04-01), None
Kim Doo-Gon
Park Ki-Tae
Auduong Gene N.
Samsung Electronics Co,. Ltd.
Volentine & Whitt PLLC
LandOfFree
Semiconductor memory device with three-dimensional array and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device with three-dimensional array and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device with three-dimensional array and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4253812