Method of testing memory cells in an address multiplexed dynamic

Details Method of testing memory cells in an address multiplexed dynamic Method of testing memory cells in an address multiplexed dynamic

1991-01-31

1992-05-26

Gossage, Glenn

Static information storage and retrieval

Read/write circuit

Testing

365193, 365233, 371 211, 371 212, G11C 2900, G11C 700

Patent

active

051173930

ABSTRACT:
An address multiplexed dynamic RAM device is provided which is capable of initiating (setting) and terminating (resetting) the test mode in response to the signal level combinations of the row address and column address strobe signals and the write enable signal. The signal level combinations employed correspond to those which are unused in the normal operating mode thereby obviating the need for providing additional external control signal terminals. In addition to writing predetermined data in selected memory cells during the test mode, verficiation of the predetermined data is also implemented during the read phase of the test mode.

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"Mitsubishi-Giho" (vol. 59, No. 9, Mitsubishi Electric Corp. 1985, pp. 60-63).

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