Multi-chip package reducing power-up peak current

Details Multi-chip package reducing power-up peak current Multi-chip package reducing power-up peak current

2008-07-22

2010-06-29

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having fuse element

C365S052000

Reexamination Certificate

active

07746719

ABSTRACT:
Disclosed is a multi-chip package having a plurality of memory chips. Each memory chip includes a memory cell array storing e-fuse data, a read-out control circuit reading e-fuse data in response to a read signal, a first internal pad receiving a first control signal, a read-out controller generating the read signal to define a read period, and to generate a second control signal following the read period, and a second internal pad receiving the second control signal, wherein the plurality of memory chips is connected series and each respective read-out control circuit and read-out controller in each one of the plurality of memory chips cooperate to implement a sequential read of e-fuse data across the plurality of memory chips.

REFERENCES:
patent: 6529407 (2003-03-01), Shukuri
patent: 6870786 (2005-03-01), Kanda et al.
patent: 7035158 (2006-04-01), Kozuka
patent: 7085181 (2006-08-01), Otsuka
patent: 2002157894 (2002-05-01), None
patent: 1019980055748 (1998-09-01), None
patent: 1019990053150 (1999-07-01), None

Affiliated with

Also associated with

Rating

Multi-chip package reducing power-up peak current does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-chip package reducing power-up peak current, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-chip package reducing power-up peak current will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4245584