Memory devices implementing clock mirroring scheme and...

Details Memory devices implementing clock mirroring scheme and... Memory devices implementing clock mirroring scheme and...

2008-03-10

2010-10-12

Sorrell, Eron J (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Peripheral configuration

C710S008000, C710S074000, C711S005000, C711S170000, C711S171000, C365S233100

Reexamination Certificate

active

07814239

ABSTRACT:
A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.

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