SOI transistor having an embedded strain layer and a reduced...

Details SOI transistor having an embedded strain layer and a reduced... SOI transistor having an embedded strain layer and a reduced...

Filed on

2006-11-28

Date issued

2010-11-09

Examiner

Landau, Matthew C (Department: 2813)

Patent Class

Semiconductor device manufacturing: process

SubClass

Making field effect device having pair of active regions...

SubSubClass

Having insulated gate

Other Related Categories

C257SE21619, C257SE21634

Type

Reexamination Certificate

Status

active

Patent number

07829421

Description

ABSTRACT:
By forming a portion of a PN junction within strained silicon/germanium material in SOI transistors with a floating body architecture, the junction leakage may be significantly increased, thereby reducing floating body effects. The positioning of a portion of the PN junction within the strained silicon/germanium material may be accomplished on the basis of implantation and anneal techniques, contrary to conventional approaches in which in situ doped silicon/germanium is epitaxially grown so as to form the deep drain and source regions. Consequently, high drive current capability may be combined with a reduction of floating body effects.

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