Method and apparatus for limiting power dissipation in test

Details Method and apparatus for limiting power dissipation in test Method and apparatus for limiting power dissipation in test

2006-12-07

2010-02-23

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07669098

ABSTRACT:
An embodiment provides a system for testing a circuit. During operation, the system scans-in input values into a first set of flip-flops. The outputs of the first set of flip-flops are coupled with the inputs of a circuit under test, the outputs of the circuit are coupled with the inputs of a set of multiplexers, and the outputs of the set of multiplexers are coupled with the inputs of a second set of flip-flops. Next, the system configures the set of multiplexers using a segment-selection circuit, which causes the outputs of the circuit to be coupled with the inputs of the second set of flip-flops. The system then captures the circuit's output values using the second set of flip-flops. Next, the system scans-out the circuit's output values using the second set of flip-flops. Finally, the system determines whether the chip has a fault using the output values.

REFERENCES:
patent: 5907562 (1999-05-01), Wrape et al.
patent: 7051255 (2006-05-01), Gschwind
patent: 7219280 (2007-05-01), McNall
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patent: 7487417 (2009-02-01), Branch et al.
patent: 2006/0107144 (2006-05-01), Saxena et al.
patent: 2007/0061647 (2007-03-01), Dhong et al.

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