Method of fabricating a trench DMOS (double diffused MOS)...

Details Method of fabricating a trench DMOS (double diffused MOS)... Method of fabricating a trench DMOS (double diffused MOS)...

2008-10-02

2010-11-02

Pham, Thanh V (Department: 2894)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S589000, C257S396000, C257S397000

Reexamination Certificate

active

07824984

ABSTRACT:
Disclosed is a method of fabricating a semiconductor device. The method can include forming a gate material layer on an inner surface of a trench which extends into a part of a semiconductor substrate by passing through an insulating layer formed on the semiconductor substrate, etching the gate material layer to an initial height in the trench above a top surface of the semiconductor substrate, etching the insulating layer such that the thickness of the insulating layer is reduced, forming a gate electrode in the trench by secondarily etching the etched gate material layer, and removing the insulating layer having the reduced thickness.

REFERENCES:
patent: 7319256 (2008-01-01), Kraft et al.
patent: 2008/0150015 (2008-06-01), Cho

Affiliated with

Also associated with

Rating

Method of fabricating a trench DMOS (double diffused MOS)... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating a trench DMOS (double diffused MOS)..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a trench DMOS (double diffused MOS)... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4224293