Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-12-23
2010-02-16
Smith, Matthew (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S283000, C257SE21176, C257SE21132
Reexamination Certificate
active
07662689
ABSTRACT:
Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.
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Intel Corporation, German Office Action mailed Jul. 20, 2007, Application No. 11 2004 002 373.4-43.
Boyanov Boyan
Chau Robert
Doyle Brian S.
Murthy Anand
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Jefferson Quovaunda
Smith Matthew
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