Semiconductor device and method for manufacturing the same

Details Semiconductor device and method for manufacturing the same Semiconductor device and method for manufacturing the same

2007-10-11

2010-06-01

Landau, Matthew C (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21636, C257SE21632, C257SE21637, C257S369000, C438S275000

Reexamination Certificate

active

07727832

ABSTRACT:
It is made possible to provide a method for manufacturing a semiconductor device that includes CMISs each having a low threshold voltage Vth and a Ni-FUSI/SiON or high-k gate insulating film structure. The method comprises: forming a p-type semiconductor region and an n-type semiconductor region insulated from each other in a substrate; forming a first and second gate insulating films on the p-type and n-type semiconductor regions, respectively; forming a first nickel silicide having a composition of Ni/Si<31/12 above the first gate insulating film, and a second nickel silicide having a composition of Ni/Si≧31/12 on the second gate insulating film; and segregating aluminum at an interface between the first nickel silicide and the first gate insulating film by diffusing aluminum through the first nickel silicide.

REFERENCES:
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patent: 2007/0145493 (2007-06-01), Koyama et al.
patent: 2007/0210351 (2007-09-01), Tsuchiya et al.
patent: 2007/0221970 (2007-09-01), Kadoshima et al.
patent: 2008/0029822 (2008-02-01), Tsuchiya et al.
Veloso et al. 2006 Symposium on VLSI Technology, Digest of Technical Papers, pp. 94-95.
Tsuchiya et al., Journal of Applied Physics, 2009, 106, 044510-1 to 044510-8.
U.S. Appl. No. 11/871,570, filed Oct. 12, 2007, to Tsuchiya et al.
Tsuchiya, Y. et al., “Practical Work Function Tuning Based on Physical and Chemical Nature of Interfacial Impurity in Ni-FUSI/SiON and HfSiON Systems,” IEDM 2006, pp. 231-234, (2006).
Takahashi, K. et al., “Dual Workfunction Ni-Silicide/HfSiON Gate Stacks by Phase-Controlled Full-Silicidation (PC-FUSI) Technique for 45nm-node LSTP and lop Devices,” IEDM Tech. Dig., pp. 91-94, (2004).
Kim, Y. H. et al., “Systematic Study of Workfunction Engineering and Scavenging Effect Using NiSi Alloy FUSI Metal Gates with Advanced Gate Stacks,” IEDM Tech. Dig., pp. 657-660, (2005).

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