Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-04-25
2010-12-28
Gaffin, Jeffrey A (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S727000, C714S729000
Reexamination Certificate
active
07861129
ABSTRACT:
An integrated circuit on a semiconductor chip with a plurality of registers distributed across the semiconductor chip. The registers are writeable and readable. The integrated circuit comprises a central control block. The integrated circuit comprises a plurality of circuit units. The circuit unit includes a functional portion with a local clock controller and one or more of the registers. The circuit unit includes a satellite portion. The central control block and the satellite portions are serially connected together and form a scan chain, wherein the scan chain is formed as a ring.
REFERENCES:
patent: 2006/0277436 (2006-12-01), McGowan
patent: 2008/0126892 (2008-05-01), Dubey et al.
Le Thuyen
Lichtenau Cedric
Padeffke Martin
Pflueger Thomas
Fleit Gibbons Gutman Bongini & Bianco PL
Gaffin Jeffrey A
Gibbons John A.
International Business Machines - Corporation
Merant Guerrier
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