Method of patterning multilayer metal gate structures for...

Details Method of patterning multilayer metal gate structures for... Method of patterning multilayer metal gate structures for...

2007-10-11

2010-10-26

Culbert, Roberts (Department: 1716)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S706000

Reexamination Certificate

active

07820555

ABSTRACT:
A method of forming patterning multilayer metal gate structures for complementary metal oxide semiconductor (CMOS) devices includes performing a first etch process to remove exposed portions of a polysilicon layer included within a gate stack, the polysilicon layer formed on a metal layer also included within the gate stack; oxidizing an exposed top portion of the metal layer following the first etch process so as to create an metal oxide layer having an etch selectivity with respect to the polysilicon layer; removing the metal oxide layer through a combination of a physical ion bombardment thereof, and the introduction of an isotropic chemical component thereto so as to prevent oxide material at bottom corners of the polysilicon layer; and performing a second etch process to remove exposed portions of the metal layer.

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Deok-Kee Kim et al.; “A study of the role of HBr and oxygen on the etch selectivity and the post-etch profile in a polysilicon/oxide etch using HBr/O2 based high density plasma for advanced DRAMs;” Materials Science in Semiconductor Processing 10 (2007) pp. 41-48.

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