Semiconductor memory device which compensates for delay time...

Details Semiconductor memory device which compensates for delay time... Semiconductor memory device which compensates for delay time...

2007-04-26

2010-02-02

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S189050, C365S154000, C365S233110

Reexamination Certificate

active

07656725

ABSTRACT:
A memory device compensates for delay time variations among multi-bit data. The device includes a first stage and a second stage of data storage units. The first stage of data storage units store first to nth data bits in response to a latch clock signal. The second stage of data storage units store the first to nth data contents output from the first stage of data storage units in response to a reference clock signal. The latch clock signal is obtained by delaying the reference clock signal. The latch clock signal includes first to nth sub latch signals. The sub latch signals are generated at different times according to propagation delay time periods of the corresponding first to nth data contents.

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