Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-07-19
2010-06-15
Ellis, Kevin L (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C716S030000
Reexamination Certificate
active
07739565
ABSTRACT:
A programmable logic device includes a configuration memory, a checker, and a redundant-logic detector. An array of programmable logic and interconnect resources is configurable to implement a selected user design. The configuration memory stores configuration data that configures the array of programmable logic and interconnect resources to implement the specified user design. A checker calculates a sequence of checksums from the configuration data that is stored in the configuration memory. A redundant-logic detector indicates corruption of the configuration data stored in the configuration memory in response to at least two consecutive checksums in the sequence not matching a reference value.
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Ellis Kevin L
Maunu LeRoy D.
Merant Guerrier
XILINX Inc.
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