Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2009-05-28
2010-10-05
Menz, Douglas M (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S258000
Reexamination Certificate
active
07807530
ABSTRACT:
Manufacturing technique for an IC device which includes forming the first conductor film over a memory cell forming region and over a peripheral circuit forming region of a semiconductor substrate, patterning the first conductive film lying over the memory cell forming region to form a first conductive pattern which serves as a first or control gate electrode of a memory cell and leaving the first conductive film over the peripheral circuit forming region, forming a second conductive film over both the memory cell forming region and the first conductive film in the peripheral circuit forming region, etching the second conductive film to form a second or memory gate electrode of the memory cell on at least a side wall of the first conductive pattern, and followed by the formation of a gate electrode of a peripheral circuit transistor by etching the first conductive film in the peripheral circuit forming region.
REFERENCES:
patent: 5296399 (1994-03-01), Park
patent: 5408115 (1995-04-01), Chang
patent: 5768192 (1998-06-01), Eitan
patent: 5852311 (1998-12-01), Kwon et al.
patent: 5966603 (1999-10-01), Eitan
patent: 5969383 (1999-10-01), Chang et al.
patent: 6011725 (2000-01-01), Eitan
patent: 6180538 (2001-01-01), Halliyal et al.
patent: 6248633 (2001-06-01), Ogura et al.
patent: 6255166 (2001-07-01), Ogura et al.
patent: 6335554 (2002-01-01), Yoshikawa
patent: 6340611 (2002-01-01), Shimizu et al.
patent: 6483749 (2002-11-01), Choi et al.
patent: 6518642 (2003-02-01), Kim et al.
patent: 6555427 (2003-04-01), Shimizu et al.
patent: 6632714 (2003-10-01), Yoshikawa
patent: 6642586 (2003-11-01), Takahashi
patent: 6818504 (2004-11-01), Rabkin et al.
patent: 6818508 (2004-11-01), Shimizu et al.
patent: 2004/0119107 (2004-06-01), Hisamoto et al.
patent: 2004/0155234 (2004-08-01), Ishimaru et al.
patent: 2004/0232471 (2004-11-01), Shukuri
patent: 1416540 (2004-05-01), None
patent: WO 03/012878 (2003-02-01), None
patent: WO 03/021666 (2003-03-01), None
patent: WO 03/028112 (2003-04-01), None
Nozaki, Takaaki et al., “A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application,” IEEE Journal of Solid State Circuits, vol. 26, No. 4, Apr. 1991 (pp. 497-501).
“Can NROM, a 2 Bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?” Eitan et al., Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials, Tokyo, 1999, pp. 522-524.
“High Speed Program/Erase Sub 100 nm MONOS Memory Cell” Fujiwara et al., pp. 75-77.
“A Novel Flash Memory Device with Split Gate Source Side Injection and ONO Charge Storage Stack (SPIN)” Chen et al., 1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 63-64.
“Twin MONOS Cell with Dual Control Gates” Hayashi et al., Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123.
Takaaki Nozaki, et al., A 1 Mbit EEPROM with MONOS Memory Cell for Semiconductor Disk Application, 1990 Symposium on VLSI Circuits, 1990 IEEE, (pp. 101-102).
Antonelli, Terry Stout & Kraus, LLP.
Menz Douglas M
Renesas Electronics Corporation
LandOfFree
Semiconductor integrated circuit device and a method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit device and a method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device and a method of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4160914