Semiconductor device with multiple silicide regions

Details Semiconductor device with multiple silicide regions Semiconductor device with multiple silicide regions

2007-03-20

2009-12-08

Dang, Trung (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S384000, C257SE29255

Reexamination Certificate

active

07629655

ABSTRACT:
A system and method for forming a semiconductor device with a reduced source/drain extension parasitic resistance is provided. An embodiment comprises implanting two metals (such as ytterbium and nickel for an NMOS transistor or platinum and nickel for a PMOS transistor) into the source/drain extensions after silicide contacts have been formed. An anneal is then performed to create a second silicide region within the source/drain extension. Optionally, a second anneal could be performed on the second silicide region to force a further reaction. This process could be performed to multiple semiconductor devices on the same substrate.

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