Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-10-07
2009-12-29
Luu, Chuong Anh (Department: 2892)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S585000, C438S157000, C438S584000
Reexamination Certificate
active
07638381
ABSTRACT:
Methods of fabricating a semiconductor structure in which a body of monocrystalline silicon is formed on a sidewall of a sacrificial mandrel and semiconductor structures made by the methods. After the body of monocrystalline silicon is formed, the sacrificial material of the mandrel is removed selective to the monocrystalline silicon of the body. The mandrel may be composed of porous silicon and the body may be fabricated using either a semiconductor-on-insulator substrate or a bulk substrate. The body may be used to fabricate a fin body of a fin-type field effect transistor.
REFERENCES:
patent: 5494837 (1996-02-01), Subramanian et al.
patent: 5952694 (1999-09-01), Miyawaki et al.
patent: 6159807 (2000-12-01), Bryant et al.
patent: 6441422 (2002-08-01), Mandelman et al.
patent: 6894310 (2005-05-01), Gonzalez et al.
patent: 6913974 (2005-07-01), Hung et al.
patent: 7259425 (2007-08-01), An et al.
patent: 7279375 (2007-10-01), Radosavljevic et al.
patent: 2007/0235734 (2007-10-01), Takafuji et al.
Edward J. Nowak et al., “Turning Silicon on its Edge. Overcoming Silicon Scaling Barriers with Double-Gate and FinFET Technology”, IEEE Circuits & Devices Magazine, Jan./Feb. 2004, pp. 20-31, USA.
N. Sato et al., “Precise Thickness control for Ultra-Thin SOI in ELTRAN® SOI-Epi™ Wafer”, 2002 IEEE International SOI Conference, 2002, pp. 209-210, Japan.
Melanie J. Sherony et al., “Reduction of Threshold Voltage Sensitivity in SOI MOSFET's”, IEEE Electron Device Letters, Mar. 1995, pp. 100-102, vol. 16, No. 3, USA.
Bin Yu et al., “FinFET Scaling to 10nm Gate Length”, 2002, pp. 251-254, Strategic Technology, Advanced Micro Devices, Inc,, Department of EECS, University of California, Berkeley, CA, USA.
D. F. Timokhov, et al., “Determination of Structure Parameters of Porous Silicon by the Photoelectric Method”, Journal of Physical Studies, 2004, pp. 173-177, vol. 8, No. 2, Odessa National University, Odessa, Ukraine.
Luu, Chuong A. (Examiner), US Patent and Trademark Office, Notice of Allowance issued in related U.S. Appl. No. 11/924,875 dated May 7, 2009.
Cheng Kangguo
Mandelman Jack Allan
International Business Machines - Corporation
Luu Chuong Anh
Wood Herron & Evans LLP
LandOfFree
Methods for fabricating a semiconductor structure using a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods for fabricating a semiconductor structure using a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for fabricating a semiconductor structure using a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4148143