Methods of forming gatelines and transistor devices

Details Methods of forming gatelines and transistor devices Methods of forming gatelines and transistor devices

2006-05-05

2009-06-09

Quach, Tuan N. (Department: 2893)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S303000, C438S585000, C257SE21409

Reexamination Certificate

active

07544554

ABSTRACT:
The invention includes semiconductor constructions, methods of forming gatelines, and methods of forming transistor structures. The invention can include, for example, a damascene method of forming a gateline. A thin segment of dielectric material is formed between two thicker segments of dielectric material, with the thin and thicker segments of dielectric material being within an opening. A gateline material is formed within the opening and over the thin and thicker segments of dielectric material. The construction comprising the gateline material over the thin and thicker segments of dielectric material can be supported by a semiconductor substrate having a primary surface which defines a horizontal direction. The thin and thicker segments of dielectric material can comprise upper surfaces substantially parallel to the primary surface of the substrate, and can join to one another at steps having primary surfaces substantially orthogonal to the primary surface of the substrate.

REFERENCES:
patent: 5434093 (1995-07-01), Chau et al.
patent: 5786256 (1998-07-01), Gardner et al.
patent: 6150669 (2000-11-01), Nandakumar et al.
patent: 6326273 (2001-12-01), Yu
patent: 6344397 (2002-02-01), Horstmann et al.
patent: 6403487 (2002-06-01), Huang et al.
patent: 6638829 (2003-10-01), Cheek et al.
patent: 6670250 (2003-12-01), Lee
patent: 6770532 (2004-08-01), Chuang et al.
patent: 6806534 (2004-10-01), Dokumaci et al.
patent: 6964875 (2005-11-01), En et al.
patent: 7183184 (2007-02-01), Doczy et al.
patent: 2002/0028568 (2002-03-01), Ueno et al.
patent: 2002/0081792 (2002-06-01), Howard et al.
patent: 2002/0130373 (2002-09-01), Ueno et al.
patent: 2002/0182794 (2002-12-01), Ning et al.
patent: 2004/0219757 (2004-11-01), Olewine et al.
patent: 2005/0287748 (2005-12-01), Kavalieros et al.
patent: 2006/0183277 (2006-08-01), Brask et al.

Affiliated with

Also associated with

Rating

Methods of forming gatelines and transistor devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods of forming gatelines and transistor devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of forming gatelines and transistor devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4148121