Memory word line driver featuring reduced power consumption

Details Memory word line driver featuring reduced power consumption Memory word line driver featuring reduced power consumption

2007-10-01

2009-12-29

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S230060

Reexamination Certificate

active

07639545

ABSTRACT:
Embodiments of a random access memory word line driver circuit that reduces consumption of standby power are described. The word line driver is based on NOR-gate logic in which, for memory array consisting of a plurality of memory cells and word line drivers, given two inputs selected one word line goes high and the rest remain zero. The decoder circuit comprises two PMOS transistors in series with an NMOS-based inverter circuit. This arrangement reduces the leakage current through the NMOS transistor when the word line is not selected. An array of word line drivers incorporating a NOR-based decoder includes a shared pull up PMOS transistor for one of two address lines. The shared pull-up PMOS transistor is manufactured to a size on the order of at least two times the width of the remaining transistors of each word line stage.

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Form PCT/ISA/220, “PCT Notification of Transmittal of The International Search Report and the Written Opinion of the International Searching Authority, or the Declaration,” 1 pgs., May 1, 2009.
Form PCT/ISA/210, “PCT International Search Report,” 3 pgs., May 1, 2009.
Form PCT/ISA/237, “PCT Written Opinion of the International Searching Authority,” 6 pgs., May 1, 2009.

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