TAP domain selection circuit with AUXI/O1 or TDI lead

Details TAP domain selection circuit with AUXI/O1 or TDI lead TAP domain selection circuit with AUXI/O1 or TDI lead

2007-12-12

2009-11-03

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07613970

ABSTRACT:
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS.41-49, provides for selectively using either the 5 signal interface of FIG.41or the 3 signal interface of FIG.8.

REFERENCES:
patent: 5222068 (1993-06-01), Burchard
patent: 6430718 (2002-08-01), Nayak
patent: 6631504 (2003-10-01), Dervisoglu et al.
patent: 2004/0044491 (2004-03-01), Yonaga et al.
patent: 2004/0177300 (2004-09-01), Biewenga et al.
“Hierarchical test access architecture for embedded cores in anintegrated circuit” by Bhattacharya, D.This paper appears in: VLSI Test Symposium, 1998. Proceedings. 16th IEEE Publication Date: Apr. 26-30, 1998 On pp. 8-14 ISBN: 0-8186-8436-4 INSPEC Accession No. 6039765.

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